1. Field of the Invention
This invention relates generally to power integrated circuits having saturating vertical output transistor configurations and, more specifically, to a method of eliminating latch-up and analog signal errors in circuits wherein the chip substrate injects current into an epitaxial layer.
2. Background Art
Recent advances in semiconductor technology includes integrated circuitry having vertical PNP output power transistors. The typical configuration comprises a P-type chip substrate, which also serves as a collector for the PNP output power transistor. An N-type epitaxial layer overlies the P-substrate and serves as a base for the PNP output power transistor as well as for lateral PNP transistors. A plurality of P-regions may be diffused into the N-type epitaxial layer. These P-regions may be used as an emitter or emitters for the PNP output power transistor, emitters and collectors of lateral PNP transistors, and resistors. This is accomplished in a manner known well by those skilled in the art.
However, there are at least three situations where the substrate would inject unwanted current into the epitaxial layer to be collected by the P-regions which may provide positive feedback to the circuit output. This positive feedback attempts to drive the substrate to a higher voltage relative to the epitaxial layer, thus injecting more current from the substrate into the epitaxial layer, creating a latch condition. Additionally, in analog circuitry, the unwanted substrate injected currents can cause circuit imbalances and major errors in analog signal paths even if a latch condition does not occur.
One example exists when the P-type substrate (circuit output) is high (at or near V.sub.CC) and the epitaxial layer is down one V.sub.BE voltage because it contains a lateral PNP transistor in a conductive condition. A second example exists when the substrate is at a high voltage level and one region of the epitaxial layer is pulled down one V.sub.BE due to lateral NPN action from adjacent epitaxial layer regions. In other words, an NPN transistor is formed by two adjacent N-type epitaxial layer regions and the P-substrate. A third example exists when the substrate voltage is above V.sub.CC due to transients on the circuit output. Under any of these examples, the substrate injects current into the epitaxial layer and any P-region diffused in the epitaxial layer may become a collector of that current.
Thus, a need exists for a method of eliminating circuit latch-up and analog signal errors in integrated circuits that comprise a substrate as the collector of a PNP power output transistor.